(1) Field of the Invention
This invention concerns chemical mechanical polishing compositions including an abrasive and cesium hydroxide. This invention also concerns methods for polishing dielectric layers associated with integrated circuits using cesium hydroxide containing polishing compositions.
(2) Description of the Art
Integrated circuits are made up of millions of active devices formed in or on a silicon substrate. The active devices, which are initially isolated from one another, are interconnected to form functional circuits and components. The devices are interconnected through the use of multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third and subsequent level of metallization. Interlevel dielectrics (ILDs) such as doped and undoped silicon dioxide (SiO2), or low-K dielectrics tantalum nitride are used to electrically isolate the different levels of metallization in a silicon substrate or well.
In typical semiconductor manufacturing processes, metallized vias, metallized layer and interlevel dielectric layers are built-up to create an integrated circuit. As the layers are being built-up, the excess materials are removed and the substrate surfaces are planarized by using chemical mechanical polishing (CMP) techniques. In a typical chemical mechanical polishing process, the substrate is placed in direct contact with a rotating polishing pad. A carrier applies pressure against the backside of the substrate. During the polishing process, the pad and table are rotated while a downward force is maintained against the substrate back. An abrasive and chemically reactive solution is applied to the pad during polishing. The slurry initiates the polishing process by chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until the desired film on the insulator is removed.
The polishing composition ingredients are an important factor in the success of the CMP step. By carefully selecting ingredients, the polishing composition can be tailored to provide effective polishing to the selected layer at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion of adjacent layers.
During the manufacture of integrated circuits, dielectric layers, typically including silicon dioxide are applied to the circuit. Once applied, the dielectric layer is generally non-planar and must be polished using a polishing composition to give a planar dielectric surface. It is important that the chosen polishing composition be capable of producing a planarized dielectric surface with few defects. Furthermore, it is important that tie polishing composition chosen be capable of polishing the dielectric layer efficiently and repeatedly. Current ILD slurries are typically stabilized abrasive slurries including about 10-30 wt % abrasives. The stabilizing ion is typically potassium or ammonia where slurries typically have a pH greater than 8. The shortcomings of potassium slurries are ionic contamination from the potassium where the contaminating ions become mobile ions and will detrimentally impact device reliability by migrating to the gate area and lowering the threshold voltage of the transistors. In addition, there is a level of defectivity that is characteristic of silica dispersed with potassium.
Ammonia slurries solve the mobile ion problem associated with potassium stabilized slurries. However, ammonia has a strong odor. In addition, ammonia slurries planarize less effectively, polish with a high level of defectivity and polish with low rates compared to potassium slurries.
As a result, there remains a need for improved polishing compositions that are capable of polishing dielectric layers efficiently to give polished dielectric layers that are essentially planar and that exhibit few defects.
In one embodiment, this invention is a chemical mechanical polishing composition comprising fumed silica and from about 0.01 to about 5.0 wt % of at least one Cs+ basic salt.
In another embodiment, this invention is a chemical mechanical polishing composition comprising water, from about 1 to about 50 wt % fumed silica, and from about 0.1 to about 2.0 wt % CsOH. The polishing composition planarizes a silicon containing substrate with an open field efficiency of at least 50% and with an array field efficiency of at least 85%.
In yet another embodiment, this invention is a chemical mechanical polishing composition capable of polishing integrated circuits having gate widths less than about 0.25 microns comprising from about 1 to about 50 wt % of a metal oxide abrasive and from about 0.01 to about 5.0 wt % Cs+ basic salt.
In still another embodiment, this invention is a method for planarizing an insulating layer with a polishing composition of this invention. The polishing is achieved by preparing a polishing composition comprising water and CsOH. The polishing composition is then applied to a surface of the substrate being planarized or to the polishing pad. The polishing pad is brought into contact with the surface of the silicon containing substrate layer being planarized, and the pad is moved in relation to the silicon containing substrate surface being planarized. An abrasive is used in conjunction with the polishing composition to facilitate polishing. The abrasive may be associated with the polishing pad or the abrasive may be added to the polishing composition to give a chemical mechanical polishing slurry before the slurry is applied to the substrate or to the polishing pad.